More on EDMA3 on the BeagleBoard/OMAP3530

Didn’t I mention that the EDMA3 on the OMAP3530 is identical to the EDMA3 of the DaVinci? As I found out this is not exactly true. There is a subtle but important difference:

The order of the transfer-controllers has been reversed. On the DaVinci TPTC0 was ment to be used for system critical controls with low latency and TPTC1 for longer background tasks. On the OMAP3530 this order is exactly reversed. And by the way: Ever wondered what the difference between those two controllers is? On the OMAP3530 the first controller has a FIFO-length of 256 bytes while the second only has 128 bytes. The transfer speed is the same, but transfers issued on the controller with the shorter FIFO have lower latency, so the data reaches the destination a tad earlier.

Btw, while I fooled around with the EDMA I made some speed measurements. I think these can be interesting..

  • DSP DMA transfer, internal to DDR2 RAM: 550 mb/s
  • DSP CPU transfer (memset) to DDR2 RAM: 123 mb/s (outch!)
  • DSP CPU transfer (memset) to internal RAM: 3550 mb/s

For reference I made the same memset test on the CortexA8:

  • CortexA8 DDR2 memset (cached): 417 mb/s
  • CortexA8 DDR2 memset (uncached): 25 mb/s

All numbers taken with GPP-clock at 500Mhz and DSP-clock at 360Mhz. Caches have been enabled and the transfer-size was one megabyte.

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